As a background art of this technical field, a graph processing method is described in Non-patent Literature 1. This Non-patent Literature 1 describes a method of converting a graph problem such as shortest path searching into a logical circuit, mounting the logical circuit on an FPGA, and performs processing. According to this method, in comparison with arithmetic processing using a CPU, processing for solving the graph problem (to be referred to graph manipulation hereinafter) can be performed at a high speed. On the other hand, according to the Non-Patent Literature 1 described above, a method in which, when a graph scale is too large to achieve a logical circuit to be mounted on an FPGA constituted by one chip, the logical circuit is divided into a plurality of FPGAs to perform the graph manipulation is described.